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Design and Performances of UHF Tag Integrated Circuits

Design of UHF RFID tag IC presents unique design challenges to satisfy constraints due mostly to the remote biaising of the batteryless tag. After a brief introduction (section 1.1) and a presentation of the architecture (section 1.2) of a tag IC, section 1.3 will show the principles of converting RF into DC via voltage multipliers successively; first in the ideal then in the real case. The end of the section will deal with the influence of the active element (the diode or the MOSFET, a comparison between the two will highlight the pros and cons of each) and passive parasitics that must be taken into account during the dimensioning of the intermediate and the output capacitors. A simplified model of the antenna and the input of the rectifier will allow us to see the importance of matching and will lead to the computation of the Power Conversion Efficiency (PCE) of the circuit. Sections 1.4 and 1.5 propose a few up-to-date circuits with careful design to reduce the threshold voltage of the active element and improve the PCE. Sections 1.6, 1.7 and 1.8 rather briefly discuss the problem of exchanging information between the reader and the tag and the improvements on the oscillator design to reduce overall consumption. Sections 1.9 and 1.10 list the latest technologies, techniques and trends used in the digital part and lists of performances of the different teams are compared.

1.1. Introduction

The ratification of the global ultra high frequency (UHF) passive radio frequency identification (RFID) standard ISO18000-6 has stimulated the interests of many research laboratories, prompting them to carry out research and development work on the UHF power rectifiers at the microwatt level. In fact, micropower rectifiers are not only limited to RFID but also useful in energy-scavenging modules for remote sensor applications [TEH 09].

The design of an integrated circuit for a UHF RFID tag is not a simple task because it requires numerous constraints to be taken into account.

The primary characteristics of an RFID tag are the cost, the communication range between the tag and the reader/writer, and the transaction time associated with the system performance. To minimize the cost, the tag should be manufactured with the tag integrated circuit (IC) and the associated antenna in a simple process; we will see later that the design rules imply both parts and then each part cannot be designed independently of the other. Despite its simple passive structure, an RFID tag should provide value-added services enabling specific RFID functions, such as data writing, the storing of historical manufacturing or distribution process data, and anticollision reads to speed up the inventory search or security functions to authenticate users [NAK 07].

First, as mentioned above, we must end up with a product for which the cost, so as not to be prohibitive for the retail RFID transponder, should be targeted at being only a few cents. Because the cost of the IC is an important part of the overall cost, it implies the choice of low-cost very large-scale integration (VLSI) technologies, which do not correspond to the best choice for some problematic designs such as the design of the rectifier. Then, a tag IC designer must deal with the challenges of low supply voltage, very low consumption, high input power dynamic range and efficient antenna matching. Because the read range is set by the forward link in a passive backscattering UHF RFID system, it means that the minimum turn-on power for the RF IC chip is of prime importance among the constraints.

A few manufacturers jealously guard their secrets about the design and fabrication process. They sell commercial products with performances as good as the ones displayed by the research laboratories. Some topics such as the optimal choice of the shunt resistor that enables the control of the received power from the far-field to the near-field are not available in the current literature but are actually implanted in certain products. This chapter aims to understand the design principles of the tag integrated circuit, especially the voltage multiplier. Some performances of the power conversion efficiency are also given with respect to different technologies and circuit topologies.

1.2. Integrated circuit architecture

A typical block diagram of a complete passive transponder architecture, including the IC and the matched antenna, is shown in Figure 1.1. Usually, we distinguish between the front-end, which is constituted of the direct current (DC) supply generation, the demodulator and the modulator and the digital part, which includes the control logic, and the electronically erasable and programmable read-only memory (EEPROM) with its charge pump.

The transponder must draw the power required for its functioning from the received electromagnetic field. This power is used mainly by the digital section (often up to 70%) and by the front-end to receive the data sent by the reader and to allow data transmission from the tag to the reader through backscattering modulation.

The regulator circuit stabilizes the output voltage of the multiplier, but it may also keep the input voltage of the multiplier below the breakdown voltage in case of a tag being close to the base station. The voltage reference is sometimes called bandgap reference and output necessary voltages (and currents sometimes) for protection (used by regulator, for example).

1.3. RF to DC conversion: modeling the system

There are two important goals for achieving high power efficiency of the transponder. The efficiency is defined as the ratio between the RF power available at the transponder’s antenna and the DC power at the output of the DC block for supplying the transponder. The first goal is the power matching between the antenna and the IC, and the second goal is the RF to DC conversion taking into account the output load constraints, namely a minimum DC voltage to operate the transponder and a minimum load current drawn by the IC (so even if the definition mentions the output power, it is important to note [BAR 09] that each parameter must be independently satisfied). So, one of the big challenges a designer must face is the design of the rectifier with high efficiency while maintaining a minimum DC output voltage and current to supply the transponder.

Figure 1.1. Architecture of a passive RFID transponder

1.3.1. Determination of the ideal DC output voltage

For UHF RFID applications requiring several meters of communication distance, the incoming signal level is only a few hundreds of mV when minimum sensitivity is considered. Therefore, only a multistage rectifier can deal with these requirements and it is used. The topology used by Dickson in 1976 has only been slightly changed by Karthaus and Fischer [KAR 03] in order to make it useful for the alternating current (AC)/DC conversion as shown in Figure 1.3.

The received AC input voltage is converted to a DC output voltage by the voltage multiplier, which is then stabilized and maintained within limits by the voltage regulator [DEV 05].

The elementary cell is built from the clamping circuit C-D1 (see Figure 1.2(a)), which shifts the negative portion of the input signal above zero by storing the equivalent electric charge on the output terminal of C1 by the charging current circulating from ground to IN through the D1 diode. Then, the rectifier circuit detects the peak value of the output signal of the clamp circuit. The electric charge previously stored is now delivered to the output capacity Cout by the charging current circulating through D2. When considering ideal elements, we can write the voltage at the output of the clamp circuit [CUR 07]:

[1.1]

where is the peak value of Vin(t), voltage at the input of the multiplier. So, in this idealized model, the maximum possible voltage at the output of the clamp circuit is 2. At the output of the rectifier circuit, this value is maintained by the parallel charged capacitor Cout.

In the real case, this value is reduced by the voltage drop of the diode.

[1.2]

where Vd is the diode drop voltage.

Besides, this value is further reduced due to imperfections of the circuit elements like the leakage current of the capacitor, the parasitic parallel resistor and the reverse current of the diode.

The half-wave voltage doubler is obtained by cascading the two circuits as illustrated in Figure 1.2(a).

To take advantage of both polarities of the input signal, we must use the full-wave voltage doubler as illustrated in Figure 1.2(b). This implies that the following voltage regulator is able to receive a differential input.

To reach the necessary output voltage (which depends on the complementary metal oxide semiconductor (CMOS) technology used but is actually approximately 1.2 V) when the tag is in the far-end, it is mandatory to use an N-stage multiplier, which consists of a cascade of N elementary cells.

Figure 1.2. Elementary cell of an N-stage multiplier: a) half-wave voltage doubler and b) full-wave voltage doubler

Figure 1.3. N-stage half-wave voltage multiplier and voltage regulator

Then the voltage generated between the input and the output for an N-stage half-wave multiplier is:

[1.3]

In the DC analysis, capacitors act as open circuits, so we now have 2N identical diodes in series; so the voltage drop across each diode may be written with respect to time as:

[1.4]

1.3.2. Determination of the “real” DC voltage

Actually, equation [1.3] is a...